AD9511BCPZ-REEL7

AD9511 is a 1.2GHz clock distribution IC, PLL core, divider, delay adjust, five output. It provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. The PLL section consists of a programmable reference divider (R); a low noise phase frequency detector (PFD), a precision charge pump and a programmable feedback divider. By connecting an external VCXO or VCO to the CLK2/CLK2B pins, frequencies up to 1.6GHz may be synchronized to the input reference. There are five independent clock outputs. Application includes low jitter, low phase noise clock distribution, clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs, high performance wireless transceivers, high performance instrumentation, broadband infrastructure.

• Low phase noise phase-locked loop core, reference input frequencies to 250MHz
• Programmable dual-modulus prescaler, programmable charge pump (CP) current
• Separate CP supply (VCPS) extends tuning range
• Two 1.6GHz, differential clock inputs, 5 programmable dividers, 1 to 32, all integers
• Phase select for output-to-output coarse delay adjust
• Fine delay adjust on 1 LVDS/CMOS output, serial control port
• Input frequency range from 0MHz to 250MHz (VS = 3.3V ± 5%, TA = 25°C)
• 4.8mA typical high value (With CPRSET = 5.1Kohm, TA = 25°C)
• 2.5% typical absolute accuracy (VCP = VCPS/2, VS = 3.3V ± 5%, TA = 25°C)
• 48 lead LFCSP package, operating temperature range from -40°C to +85°C

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