MT28EW128ABA1HPC-0SIT

MT28EW128ABA1HPC-0SIT is a parallel NOR flash embedded memory. It is an asynchronous, uniform block, parallel NOR Flash memory device. READ, ERASE, and PROGRAM operations are performed using a single low-voltage supply. Upon power-up, the device defaults to read array mode. The main memory array is divided into uniform blocks that can be erased independently so that valid data can be preserved while old data is purged. PROGRAM and ERASE commands are written to the command interface of the memory. An on-chip program/erase controller simplifies the process of programming or erasing the memory by taking care of all special operations required to update the memory contents. The end of a PROGRAM or ERASE operation can be detected and any error condition can be identified. The command set required to control the device is consistent with JEDEC standards.

• Voltage range from 2.7 to 3.6V VCC core, 128Mb density, single die stack, 2nd generation
• Die Rev A, x8, x16 configuration, high lock block structure, standard default security
• Single-level cell (SLC) process technology
• Supply voltage range from 2.7 to 3.6V (program, erase, read), 1.65 - VCC (I/O buffers)
• Page size: 16 words or 32 bytes, page access: 20ns, random access: 70ns (VCC = VCCQ = 2.7-3.6V)
• 2.0MB/s (TYP) when using full buffer program, 2.5MB/s (TYP) when using accelerated buffer program
• Word/Byte program: 25us per word (TYP), block erase (128KB): 0.2s (TYP)
• Read from another block during a PROGRAM SUSPEND operation
• Unlock bypass, block erase, chip erase, and write to buffer capability
• 64-ball LBGA package, ambient operating temperature range from -40°C to +85°C