HEF4021BP

The HEF4021BP is a 8bit static Shift Register with a synchronous serial data input (DS), a clock input (CP) and an asynchronous active high parallel load input (PL), eight asynchronous parallel data inputs (D0 to D7) and buffered parallel outputs from the last three stages (Q5 to Q7). Each register stage is a D-type flip-flop with a set direct (SD) and clear direct (CD) input. Information on D0 to D7 is asynchronously loaded into the register while PL is high, independent of CP and DS. When PL is low, data on DS is shifted into the first register position and all the data in the register is shifted one position to the right on the low-to-high transition of CP. Schmitt trigger action makes the clock input highly tolerant of slower rise and fall times.

• Tolerant of slower rise and fall times
• Fully static operation
• Standardized symmetrical output characteristics
• Complies with JEDEC standard JESD 13-B