AD9231BCPZ-40

AD9231 is a monolithic, dual-channel, 12bit, 40MSPS ADC. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the SPI. A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance. Typical applications include communications, diversity radio systems, multimode digital receivers (GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA), I/Q demodulation systems, smart antenna systems, battery-powered instruments, handheld scope meters, portable medical imaging, ultrasound, Radar/LIDAR.

• 1.8V analogue supply operation and 1.8V to 3.3V output supply
• SNR of 71.5ddBFS at 9.7MHz input and 69dBFS at 200MHz input
• SFDR of 95dBc at 9.7MHz input and 83dBc at 200MHz input
• 37mW standby power and 2.2mW power-down power
• Differential input with 700MHz bandwidth
• On-chip voltage reference and sample-and-hold circuit
• 2V p-p differential and optional clock duty cycle stabilizer
• Offset binary, grey code, or twos complement data format and energy-saving power-down modes
• Integer 1-to-8 input clock divider and data clock out with programmable clock and data
• 64 lead LFCSP-VQ-EP package, operating temperature range from -40°C to 85°C

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