AD9645BCPZ-125

AD9645BCPZ-125 is a dual channel, 14-bit, 125MSPS analogue-to-digital converter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock output (DCO) for capturing data on the output and a frame clock output (FCO) for signalling a new output byte are provided. The ADC provides several features designed to maximize flexibility and minimize system cost, such as programmable output clock and data alignment and digital test pattern generation. It is used in applications such as communications, diversity radio and smart antenna systems, multimode digital receivers, GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA, I/Q demodulation systems, broadband data applications, battery-powered instruments, handheld scope meters, portable medical imaging and ultrasound, radar/LIDAR.

• Full chip and individual channel power-down modes, flexible bit orientation
• Built-in and custom digital test pattern generation, clock divider
• Programmable output clock and data alignment, programmable output resolution, standby mode
• Gain error is -1.5% FSR typical at (AVDD = 1.8V, DRVDD = 1.8V)
• Differential nonlinearity is +1.3LSB maximum at (AVDD = 1.8V, DRVDD = 1.8V)
• Offset error is 3.3ppm/°C typical at (AVDD = 1.8V, DRVDD = 1.8V)
• Analog input bandwidth is 650MHz typical at (AVDD = 1.8V, DRVDD = 1.8V)
• 2V p-p input voltage range, 1.8V supply operation, AEC-Q100 qualified for automotive applications
• Signal to noise ratio is 74.3dBFS typical at (AVDD = 1.8V, DRVDD = 1.8V)
• Operating temperature range from -40°C to +85°C, 32-lead LFCSP package

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