ADP7182AUJZ-5.0-R7

ADP7182 is a CMOS, low dropout (LDO) linear regulator. Using an advanced proprietary architecture, it provides high power supply rejection and low noise, and achieves excellent line and load transient response with a small 2.2μF ceramic output capacitor. The device regulator output noise is 18μV rms independent of the output voltage. The enable logic is capable of interfacing with positive or negative logic levels for maximum flexibility. It is widely used in application such as regulation to noise sensitive applications, analogue-to-digital converter (ADC) and digital-to-analogue converter (DAC) circuits, precision amplifiers, communications and infrastructure, medical and healthcare, industrial and instrumentation etc.

• Power supply rejection ratio (PSRR) is 66dB at (10kHz, VIN = −6V, VOUT = −5V)
• Positive or negative enable logic, output voltage is −5V
• Input voltage range is −2.7V to −28V
• Output current is −200mA max, supported by ADIsimPower tool
• Low dropout voltage is −185mV typ at −200mA load
• Initial accuracy is ±1%, accuracy over line, load, and temperature is +2% max/−3% min
• Low quiescent current is −650μA typ with −200mA load, low shutdown current is −2μA typ
• Current-limit and thermal overload protection
• Operating temperature range is −40°C to +125°C
• Packaging style is 5-lead TSOT

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