ATSAMA5D35A-CU

The SAMA5D3 series high-performance power-efficient Embedded MPU based on the ARM® Cortex®-A5 processor, achieving 536MHz with power consumption levels below 0.5mW in low-power mode. The device features a floating point unit for high-precision computing and accelerated data processing and a high data bandwidth architecture. It integrates advanced user interface and connectivity peripherals and security features. The SAMA5D3 series features an internal multi-layer bus architecture associated with 39 DMA channels to sustain the high bandwidth required by the processor and the high-speed peripherals. The device offers support for DDR2/LPDDR/LPDDR2 and MLC NAND Flash memory with 24-bit ECC. The comprehensive peripheral set includes an LCD controller with overlays for hardware-accelerated image composition, a touchscreen interface and a CMOS sensor interface. Connectivity peripherals include Gigabit EMAC with IEEE1588, 10/100Mbps EMAC, multiple CAN, UART SPI and I²C.

• ARM Cortex-A5 processor with ARMv7-A thumb-2 instruction set
• 32KB data cache, 32kB instruction cache, virtual memory system architecture (VMSA)
• Fully integrated MMU and floating point unit (VFPv4)
• System running up to 166MHz
• Reset controller, shutdown controller, periodic interval timer, watchdog timer and real-time clock
• Internal low-power 32kHz RC oscillator and fast 12MHz RC oscillator
• 39 DMA channels including two 8-channel 64-bit central DMA controllers
• 64-bit advanced interrupt controller
• Three programmable external clock signals
• Programmable fuse box with 256 fuse bits (of which 192 are available for users)
• Low power management - Shutdown controller, clock generator and power management controller
• One 10/100/1000Mbps Gigabit Ethernet media access controller (GMAC) with IEEE1588 support
• One 10/100Mbps Ethernet media access controller (EMAC)
• Two CAN controllers with 8 mailboxes, fully compliant with CAN 2.0 part A and 2.0 part B
• Softmodem interface
• Three high speed memory card hosts (eMMC 4.3 and SD 2.0)
• Serial peripheral interface (SPI)
• Two synchronous serial controllers
• 3 two-wire interface up to 400kB supporting I²C protocol and SMBUS
• Safety - power-ON reset cells, independent watchdog and main crystal clock failure detection
• Five 32bit parallel input/output controllers
• Input change interrupts capability on each I/O line, selectable Schmitt trigger input
• Slew rate control on high speed I/Os
• Impedance control on DDR I/Os