MT53E256M32D2DS-053 WT:B

MT53E256M32D2DS-053 WT:B is a 8Gb mobile low-power DDR4 SDRAM with low VDDQ (LPDDR4). It is a high-speed CMOS, dynamic random-access memory. The device is internally configured with x16 I/O, 8-banks. Each of the x16’s 536,870,912bit banks is organized as 32,768 rows by 1024 columns by 16bits.

• 1.10V VDD2/0.60V or 1.10V VDDQ operating voltage range, 256 Meg x 32 configuration
• LPDDR4, 2 die count, 535ps, tCK RL = 32/36 cycle time
• 8Gb total density, 3733Mb/s data rate per pin
• 16n prefetch DDR architecture, 8 internal banks per channel for concurrent operation
• Single-data-rate CMD/ADR entry, bidirectional/differential data strobe per byte lane
• Programmable READ and WRITE latencies, programmable and on-the-fly burst lengths
• On-chip temperature sensor to control self refresh rate
• Partial-array self refresh, selectable output drive strength, clock-stop capability
• Directed per-bank refresh for concurrent bank operation and ease of command scheduling
• 200-ball WFBGA package, operating temperature range from -30°C to +85°C

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